module traffic2(CLK,RESET,AG,AY,AR,BG,BY,BR,TC,UP,DOWN);input CLK,RESET,UP,DOWN,TC;output AG,AY,AR,BG,BY,BR;reg AG,AY,AR,BG,BY,BR;reg [3:0]Timer,Timer2,TimerY;wire Timer1;wire Ta,Tb,Ty;reg St;reg [1:0]CurrentState,NextState;parameter S0=2'b00,S1=2'b01,S2=2'b11,S3=2'b10;always@(posedge CLK or negedge RESET)begin:stateregif(~RESET) CurrentState<=S0;else CurrentState<=NextState;endalways@(CurrentState or Ta or Tb or Ty)begin:fsmcase(CurrentState)S0:beginNextState=(~Ta)?S1:S0;St=(~Ta)?1:0;endS1:beginNextState=(~Ty)?S2:S1;St=(~Ty)?1:0;endS2:beginNextState=(~Tb)?S3:S2;St=(~Tb)?1:0;endS3:beginNextState=(~Ty)?S0:S3;St=(~Ty)?1:0;endendcaseendassign Timer1=9; always@(posedge CLK or posedge EN or negedge RESET or posedge TC )begin:counterif((EN)&&(Timer2==0))begin:Timer2<=Timer1;Timer<=Timer1;endelse if(~RESET)begin:Timer2<=Timer1;Timer<=Timer1;endelse if(TC)begin:if(UP)Timer2<=Timer2+1'b1;else if(DOWN)Timer2<=Timer2-1'b1;endelse if(St)Timer<=Timer2;else Timer<=Timer-1;endassign Ta=Timer;assign Tb=Timer;always@(posedge CLK or negedge RESET)begin:TYcounterif(~RESET)TimerY<=4'b0101;else if(St)TimerY<=4'b0101;else TimerY<=TimerY-1'b1;endassign Ty=TimerY;always@(CurrentState)begincase(CurrentState)S0:begin{AG,AY,AR}=3'b100;{BG,BY,BR}=3'b001;endS1:begin{AG,AY,AR}=3'b010;{BG,BY,BR}=3'b001;end S2:begin{AG,AY,AR}=3'b001;{BG,BY,BR}=3'b100;endS3:begin{AG,AY,AR}=3'b001;{BG,BY,BR}=3'b010;endendcaseendendmoduleError (10170): Verilog HDL syntax error at traffic2.v(59) near text "<="; expecting ";", or "@", or "end", or an identifier, or a system task, or "{", or a sequential statementError (10149): Verilog HDL Declaration error at traffic2.v(64): identifier "Timer2" is already declared in the present scope